Static RAMs (SRAM) are fast, low power and easier to use in the microprocessor system since they are unlikely that operates in dynamic RAMs, they require no refresh circuit. Hence SRAMs are often preferred as main memory in high performance small system, where their inherently high speed permits operation without a cache. Further, their low standby power, are used extensively for battery back up and in battery operated power. Furthermore, in the field of personal computer, the SRAM cells serve as the cache memory to reduce the number of wait states with the system processor.
FIG. 1 shows a conventional four-transistor and two-poly-load SRAM cell 5 having two access transistors 11 and 12 which connect respective nodes N1 and N2 to respective bit lines 21 and 22. The poly loads 31 and 32 and transistors 41 and 42 control the voltages on nodes N1 and N2. The poly loads 31 and 32 are between respective nodes N1 and N2 and a supply voltage V.sub.CC. The transistors 41 and 42 are between respective nodes N1 and N2 and ground (reference voltage VSS) and have gate cross-coupled to opposite nodes N2 and N1, respectively.
In the steady state, the voltages on nodes N1 and N2 are complementary. Voltage on node N1 being high turns on transistor 42, which pull down node N2 low. When the voltage on node N2 is low, transistor 41 is off so that the node N1 is high. Thus a bit data is latched or say stored in SRAM cell 5. During a write cycle, a gate voltage on word line 10 turns on the access transistor 11 and 12. A low voltage asserted the bit line 21 switches the voltage levels on the latch and as a consequence can switch the state of the cell.
It is noted that the stand-by current I.sub.1 and I.sub.2 will keep, however, at certain current level i.e. I.sub.1 =(V.sub.CC -V.sub.DS)/R.sub.1, and I.sub.2 =(V.sub.CC -V.sub.TH)/R.sub.2, for the situation that the transistor 42 turns on, but the transistor 41 turns off. Hence, for the purpose of further reduce the current consumption, it is required to increase the resistance of poly loads, but it will cause the instability issue for retaining the data in the cell. A high performance poly load to resolve above issue, therefore, is sought.